Microchip Market Dynamics – Consumer Electronics

Expert Profile

Section 1: Microchip Design & Value Creation

1.1. What is your current design philosophy behind your microchips?

There are two philosophies behind consumer devices. One is the high-end market, and the other is the embedded industry that falls into automotive, IOT, even mobile in some ways. However, it’s a lot more pervasive than that and they both affect consumer electronics.

At the high end, you think about server, desktop computing, laptop computing, general purpose computing devices, those are the areas that you find the traditional name stakes in microchips. In this space, you’re going to see Intel, AMD, NVIDIA, and so on. There are a plethora of other companies that manufacturer chips in that vein.

When you get into the embedded industry it includes the huge mobile market with a market drive of five billion devices a year; you also include the embedded market, which is upwards of 10 billion devices a year. In these markets, it’s a lot more pervasive for microchip manufacturers to penetrate that market. An example there is, you might have about 120 different chip manufacturers in the embedded, mobile, automotive and streaming appliance industry, whereas you might have five namesakes in the PC industry.

The general thinking for the high-end market is that they continue to struggle with transistor density. They struggle with the traditional KPIs of power, cost, and performance. Those are the three main factors there in general compute.

The other end of the market, which is more of the embedded industry, they have room to grow. They haven’t fully saturated or made use of Moore’s Law and transistor density and Dennard Scaling power density. There’s actual room to grow there. You’re going to find that PCs, for example, have been in a race for speed, power, and performance by capitalizing on Moore’s Law of scaling. Take the new Apple M1 chip that they produced. It’s going to be using the most aggressive process nodes, the bleeding edge of fabrication technology, and include billions of transistors. They have to do that to meet and beat Moore’s Law of scaling. If you look at, say a set-top box or an embedded device in a smart-doorbell (like Ring), they are going to use a process node that’s several generations behind general purpose computing. In this example, there is room to grow and capitalize on power, performance, and density improvements.

1.2. How do you design microchips to meet demands for the market?

First, there’s a number of KPIs here that have to be talked about and some of them are going to be feature-driven. You want to amortize your chip design as long as possible, and you might have to have a guaranteed availability of supply in some industries of up to 15 years. But other factors are going to be performance, power, and cost. That’s always a driving factor. Other factors include progressing with new standards, interfaces, and features that are progressing in other industries. For example, the industry has moved from SATA hard disk interfaces to NVMe. That requires new silicon to interface to faster storage. But when you look at a new chip design, you’re going to start by what are the trends and what are the standards that I need to fulfill for my customers?

You’re looking at things like new bus architectures or new memory interfaces and new wireless protocols, like 802.11ax or Bluetooth. You’re also going to be looking at some of the forcing functions from your marketing, software teams, and industry. Machine learning, particularly inference engines for machine vision are becoming a necessary and standard feature in desktop and mobile systems. The Apple M1 core has a huge amount of silicon area dedicated to machine learning inference to address this growing market demand. You also will examine emerging technologies like new encryption engines in silicon, new video and audio compressors (CODECs), and other emerging standard for hardware acceleration. There may be a forcing function where certain markets, such as YouTube or Google might be requiring partners to use certain codecs for audio and video compatibility.

1.3. What new technologies have you built into your microchips?

Having worked on both high-end and low-end chip sets, one of the things that I would mention is embracing the latest nodes and process nodes. Being on an aggressive node achieves a couple things. When you fabricate to the latest nodes, you can get a larger chip density on a die and you can save cost, but you have to balance that cost because it’s usually 30% more expensive to reduce a node from a fab manufacturing standpoint.

The other thing that you can do is increase performance or decrease power. Those are two knobs that you can play with when you look at the fab.

Other things that you’re going to look at is how the device is packaged. That’s going to become increasingly important thing as we are nearing the edge of Moore’s Law and what it can give us. I think we’re going to be talking about that in the future, but packaging is important now as well.

Battery-based devices are going to be power driven and things that can source power are going to be more performance driven. So, it’s really two different markets. In the general computing, PC and laptop space, there’s a kind of balance there because you want to have longest battery life. You actually play with some knobs to give you the best average power, best average performance. That’s how Intel and AMD had been producing chips sets for a number of years in that space, consumer space.

Other trends are in the design and layout of chip design. Chiplet design is now mainstream. I first designed silicon devices using chiplet concepts over 15 years ago. Chiplet based design divides the chip into partitions that can be isolated, powered differently, and reduces test and qualification time. This is in contrast to monolithic chips that simply place transistors and circuits anywhere within the die. Now large silicon providers have migrated to chiplet design.

1.4. What is the future of microchip design in the next 5-10 years?

People have been predicting the end of Moore’s Law for 20 years. There is a saying in the industry that the end of Moore’s Law is always 20 years away.

First, I think that within five years, we’ll be moving from five nanometer to three nanometer designs. That’s going to reach density and there’s really only three fab manufacturers that can really entertain those nodes right now, the leading manufacturer being TSMC, then Samsung, then probably Global Foundries.

The other things that are going to be important is when you scale down to three nanometers, everything is using EUV lithography. That allows you to actually reduce some of the mask steps. There could be some cost savings there as you can pack more dies onto a wafer.

When you scale down below three nanometers at a fab, things are going to get a lot more complex. This is where it’s going to be prohibitively expensive to scale Moore’s Law any further and you enter the realm of quantum dynamics in some respects. There are some techniques and trends that are hot topics in the semi-industry. Experimental stuff, research stuff to drive process nodes or density further. For example, we could see the advent of nano printing. Instead of using a lithography process, you’re using a printed or a pressed type of arrangement to develop the die.

After that, you have to start looking at things like nanowires, that you can actually move away from finFETs in the way that they’re designed and build transistors using these very small nanowires that push through the substrate. That gives you a 2x density improvement. After that, you want to look at stacking nanowires and adding 3D elements to things, and that’s going to be really important.

This touches on the packaging, because to improve and be higher in density five years from now, we’re going to have to look at techniques like wafer-to-wafer stacking or die- stacking. Regardless packaging is going to be just a huge challenge. There is only so far you can go with ceramic packaging and cooling solution. As you drive more transistors into a smaller area the thermal transfer becomes a gating function. I think that’s going to be very interesting in five years.

1.4.1. How will Apple handle the end of Moore’s law?

They’re going to have the same physical challenges as anyone else. I believe that the next set of advances are going to be in packaging, into very advanced chip packaging. Interposers, die bonding, hybrid bonding, and now wafer-level of processing. Techniques like that are going to have to be employed and that is not necessarily what Apple is going to be doing. Apple is a chip designer now. Like other chip designers you start with an architecture definition and end with a netlist that delivered to TSMC. Any of the fab manufacturers are going to take a more profound or pronounced role in future semiconductors, packaging companies, companies that can deal with interposers and hybrid bonding and stuff like that.

Section 2: Microchip Manufacturing & Production Cost Cutting

2.1. How has the COV-19 pandemic impacted your manufacturing process?

The process itself, no. There are three things that are contributing, in my opinion, to the shortage.

One is just general logistics, simply moving freight. You’re moving it from different international fabs to distribution centers or final assembly centers or packaging centers. A fabrication process for a single chip can take two months of fab time, but it utilizes a plethora of different chemicals, substrate material, and rare earth compounds. All that material must move into and out of fabs smoothly. That has been in existence because there’s been a backlog in freight in general.

The second component here is the timing. Apple and other entities saturated the market or saturated the fab capacity in a very short amount of time which has created a backlog and time to market issues for everyone else.

The third issue that I can speculate on, is the water issue in Taiwan. I think all three of those are contributing factors to a very lean process that doesn’t have a large margin for error.

Overall, I don’t think that there’s going to be an inflationary effect. There’s going to be issues that can be remediated through doing lifetime buys, but there could be delays in shipment in the auto industry which is what you’re seeing now in the auto industry.

2.2. What are the implications for creating an E2E manufacturing process?

I don’t think it would be a complete end-to-end process. Take Apple, they started their venture in silicon design about 15 years ago, when they acquired PA Semi in Santa Clara. That was the first time that they brought into a real chip designer house. Before that, they were completely reliant on, for example, Samsung building a lot of their chips. Their first mission was to create the Apple A1 core for their iPods. Subsequently, they built onto that architecture for the iPhone. The same team, as well as other strategic acquisitions, now have built a CPU for general purpose computing. A general computing device that is as powerful, if not more powerful, than what Intel can produce. Their manufacturing ends at the netlist, what you’re going to hand off, basically a set of geometries, to a fab.

In a traditional chip design flow, I brought in teams that have had to build a chip from scratch and you can look at your value add. If I have some intellectual property or I have an algorithm and I need to put it in hardware, I can do that. I can code that up, simulate it and I can push it off to a backend provider like Microsemi. They’ll have a contractual design house that’ll take that IP that I developed and make sure that its routes. So, they do what’s called placing a routing, and they’re going to ensure all the timing is met.

They’re going to make sure that you can take your algorithm, that describes a circuit and make it work in silicon. At that point, they’re going to hand it to a fab. That’s the third party that could be involved, and the fab would, like in the latest nodes, are going to be Global Foundries, Samsung, or TSMC. After that, the fab or a packaging house will take die cuts and basically bond them into a ceramic package.

Those are usually the four steps. What Apple has done is that they’ve combined those first two steps. They may have some IP that they buy, or they might have a partner that contributes to some of it, but they do all of their IP design, as well as their placing routing in-house.

I do not see a time when any chip manufacturer, except for Intel, and of course, memory manufacturers like Micron, will incorporate full E2E. Fabrication is an enormously capital-intensive task and you always have to be chasing the latest node so it’s just a capital sink. Unless you’re like Intel and you’ve embraced that philosophy for the last 50 years or Micron, which is a memory manufacturer, I don’t foresee a time when you’re going to see, for example, Google, designing their own chip as well as fabricating it.

2.3. How do you scale your production process?

More fab space, helps, and also, chasing the latest node allows you to combine more chips within a wafer. Now, the issue with that is, every time you reduce the node size, the IP designers are just adding more circuits, so you’re actually just consuming that density. The other thing is that there still is a lot of capacity out there, if you don’t need to be at the latest node. A lot of IOT devices and embedded devices don’t necessarily have to be at the most egregious node to capitalize on it.

2.4. How can producers cut their production costs?

2.4.1. AI tools to identify cost savings

Manufacturer’s production cost is tied to yield and what a lot of manufacturers are doing now is trying to identify yield loss earlier than after the full shuttle run is done in a fab and they’re using a lot more advanced AI to actually do inspections of wafers as they’re being produced and to try to treat that as an agile process, where you can do it in time-of-flight. This is one way to cut production costs and there are some AI tricks there that are used.

2.4.2. Process evolution and improvements

Usually when you move to the most egregious node, you’re going to have some pretty high yield losses, but as the process evolves over time, your yield loss improves. This is a tried-and-true mechanism in the industry for a long time. I anticipate that they’ll just keep doing the same thing. I do see machine learning and computer vision; subatomic computer vision techniques being used more often now.

2.4.3. Increasing fab capacity

I think increasing our fab capacity and building fabs in different regions will certainly help. I think that’s a necessary component to some of our capacity issues right now. I think some of the other techniques that I alluded to are more in the research phase, such as on nano imprinting, techniques like that can actually save some of the fab cost. But the big thing right now is, as the industry has moved to 10 nanometer and then 7 nanometer and so on, what’s interesting is that you necessarily had to go to ultraviolet, extreme ultraviolet, lithography to do that. One benefit in doing that is that it has reduced mask steps. So, there’s process time, there’s less cost, there’s less process steps, less time. You can only do that for so far, but it’s a little better than the older wet lithography techniques.